`include "define.v"
module pipeCntl(
                     
output F_stall,
output F_bubble,
output D_stall,
output D_bubble,
output E_stall,
output E_bubble,
output M_stall,
output M_bubble,
output W_stall,
output W_bubble,
                     
input  [3:0] d_opcode,
input  [3:0] d_srcA,
input  [3:0] d_srcB,
input  [3:0] e_opcode,
input  [3:0] e_dstM,
input  e_cnd,
input  [3:0] m_opcode,
input  [2:0]m_stat,
input  [3:0] w_opcode,
input  [2:0] w_stat
		 );
assign F_stall=((e_opcode=={`NORM_INS,`MRMOV16} || e_opcode=={`NORM_INS,`MRMOV32}|| e_opcode=={`NORM_INS,`POP})&&(e_dstM==d_srcA||e_dstM==d_srcB))
||(d_opcode=={`NORM_INS,`RET}||e_opcode=={`NORM_INS,`RET} || m_opcode=={`NORM_INS,`RET})
?1'b1:1'b0;
assign D_stall=((e_opcode=={`NORM_INS,`MRMOV16} || e_opcode=={`NORM_INS,`MRMOV32}||e_opcode=={`NORM_INS,`POP})&&(e_dstM==d_srcA||e_dstM==d_srcB))
?1'b1:1'b0;
assign D_bubble=    
    ((e_opcode[7:4]=={`NORM_INS,`GROUP_JMP}&& !e_cnd)||(d_opcode=={`NORM_INS,`RET}||e_opcode=={`NORM_INS,`RET}||m_opcode=={`NORM_INS,`RET}))
      ?1'b1:1'b0; 

      //Why????=====================
assign E_bubble=((e_opcode[7:4]=={`NORM_INS,`GROUP_JMP}&& !e_cnd)
||((e_opcode=={`NORM_INS,`MRMOV16} || e_opcode=={`NORM_INS,`MRMOV32}||e_opcode=={`NORM_INS,`POP})&&(e_dstM==d_srcA||e_dstM==d_srcB)))
?1'b1:1'b0;
assign F_bubble=0;

assign E_stall=0;
assign M_bubble=0;
assign M_stall=0;
assign W_bubble=0;
assign W_stall=0;

endmodule
